RustでRISC-Vエミュレータを書いてNOMMU Linuxをブラウザで動かした #

pub struct Cpu<B> {
    /// CPU bus
    bus: B,
    /// Registers
    x: [u32; 32],
    /// Program counter
    pc: u32,
}

pub trait BusReader {
    fn read8(&self, addr: u32) -> Result<u8, BusException>;
    fn read16(&self, addr: u32) -> Result<u16, BusException>;
    fn read32(&self, addr: u32) -> Result<u32, BusException>;
}

impl<B: BusReader> Cpu<B> {
    pub fn step(&mut self) {
      // 1~4までを実施する
    }
}

loop {  
    match core.step() {   
        CpuState::Active if core.bus().power_off() => return,
        CpuState::Active if core.bus().reboot() => break 'reboot,
        CpuState::Idle => {
            sleep(core::time::Duration::from_micros(100));
            core.add_cycles(1);
        }
        _ => {}
    }  
}  

let Ok(ir) = self.bus.read32(self.pc) else { ... }

pub struct Bus {
    pub ram: Vec<u8>,
}

impl BusReader for Bus {
    fn read32(&self, addr: u32) -> Result<u32, BusException> {
      let addr = addr.wrapping_sub(RAM_START);
      Ok(u32::from_le_bytes([
          self.ram[addr as usize],
          self.ram[addr as usize + 1],
          self.ram[addr as usize + 2],
          self.ram[addr as usize + 3],
      ]))
    }
}

let Ok(ir) = self.bus.read32(self.pc) else { ... }

fn step(&mut self) {
  // ...
  match ir & 0x7f {
    0b0010011=> self.op(ir),
    _ => {
        todo!("Other instructions")
    }
  }
}

fn op(&mut self, ir: u32) {
    // funct3を判別する
    match (ir >> 12) & 7 {
        0b000 => // Please impl ADDI,
        _ => {
          todo!("Other instructions")
        }
    }
}

fn op(&mut self, ir: u32) {
    // irからI形式にもとづきrdを取り出す
    let rd = helpers::rd(ir);
    // irからI形式にもとづき即値を取り出す
    let imm = ir >> 20;
    let imm = imm | if (imm & 0x800) != 0 { 0xfffff000 } else { 0 };
    // irからI形式にもとづきrｓ１を取り出す
    let rs1 = self.x[helpers::rs1(ir)];
    let v = match (ir >> 12) & 7 {
        // funct3を判別し、対応する演算を行う。以下は加算。
        0b000 => rs1.wrapping_add(imm),
        _ => {
          todo!()
        }
    };
}

  fn op(&mut self, ir: u32) { 
        let rd = helpers::rd(ir); 
        let imm = ir >> 20; 
        let imm = imm | if (imm & 0x800) != 0 { 0xfffff000 } else { 0 };  
        let rs1 = self.x[helpers::rs1(ir)];
        let v = match (ir >> 12) & 7 { 
            0b000 => rs1.wrapping_add(imm), 
            _ => todo!(),
        }; 
        // rdに書き戻す。この例ではx14に書き戻す 
        self.write_back(rd, v) 
    }

fn op(&mut self, ir: u32) { 
    let rd = helpers::rd(ir);
    let imm = ir >> 20;
    let imm = imm | if (imm & 0x800) != 0 { 0xfffff000 } else { 0 };
    let rs1 = self.x[helpers::rs1(ir)];
    let reg = (ir & 0b100000) != 0;
    let rs2 = if reg { self.x[imm as usize & 0x1f] } else { imm };
    let v = match (ir >> 12) & 7 {  
        0b000 if reg && (ir & 0x4000_0000) != 0 => rs1.wrapping_sub(rs2), 
        0b000 => rs1.wrapping_add(rs2), 
        0b001 => rs1 << (rs2 & 0x1f), 
        0b010 => ((rs1 as i32) < (rs2 as i32)) as u32, 
        0b011 => (rs1 < rs2) as u32, 
        0b100 => rs1 ^ rs2, 
        0b101 if (ir & 0x40000000) != 0 => ((rs1 as i32) >> (rs2 & 0x1f)) as u32, 
        0b101 => rs1 >> (rs2 & 0x1f), 
        0b110 => rs1 | rs2, 
        0b111 => rs1 & rs2, 
        _ => { 
            self.record_exception(Exception::IllegalInstruction, ir); 
            0 
        } 
    }; 
    self.write_back(rd, v)
}

pub struct Clint<T> {
    /// Machine-mode software interrupts are generated by writing to the memory-mapped control register msip
    /// The msip register is a 32-bit wide WARL register where the upper 31 bits are tied to 0.
    /// The least significant bit can be used to drive the MSIP bit of the mip CSR of a RISC-V hart.
    /// Other bits in the msip register are hardwired to zero. On reset, the msip register is cleared to zero.
    pub msip: u32,
    /// This is a read-write register and holds a 64-bit value.
    /// A timer interrupt is pending whenever mtime is greater than or equal to the value in the mtimecmp register.
    /// The timer interrupt is used to drive the MTIP bit of the mip CSR of a RISC-V core.
    pub mtimecmp: u64,
    /// mtime is a 64-bit read-write register that keeps track of the number of cycles counted from an Arbitrary
    /// point in time. It is a free-running counter which is incremented every tick_count number of cycles
    pub mtime: u64,
    /// timer driver.
    timer: T,
}

impl<T: TimerDriver> Clint<T> {
  pub fn step(&mut self, mip: &mut u32) {
      // 経過時間を加算する
      // 実際の実装は以下
      // https://github.com/bokuweb/r2/blob/main/devices/src/timer.rs#L14
      self.mtime += self.timer.as_micros();
      // 割り込み発生条件を満たしていたらCPUのMTIP（bit 7）：Machine timer interrupt pendingを立てる
      if self.mtimecmp != 0 && self.mtime >= self.mtimecmp {
          *mip |= 0x80;
      } else {
          *mip &= !(0x80);
      }
  }
}

pub fn step(&mut self) {
  // Drive bus state
  self.bus.step(&mut self.mip);
  // bit3 in mstatus is MIE: Machine Interrupt Enable
  if (self.mip & 0x80 != 0) && (self.mie & 0x80 != 0) && (self.mstatus & 0x8 != 0) {
      self.exception = Interrupt::MachineTimerInterrupt.into();
      // ここで割り込み処理をおこなう
      self.process_exception();
      return CpuState::Active;
  }
}

fn process_exception(&mut self) {
  // 割り込みや例外の要因はmcauseに保存する
  self.mcause = self.exception;
  self.mtval = 0;
  // mepcには割り込み前のpcを保存しておく
  self.mepc = self.pc;
  let prev: u32 = self.previous_mode.into();
  // mstatusにprevious_modeを保存しておく
  self.mstatus = (((self.mstatus) & 0x08) << 4) | (prev << 11);
  // vectorへジャンプする
  self.pc = self.mtvec;
  self.previous_mode = PrivilegeMode::Machine;
  self.exception = 0;
}

pub struct Bus<T, S> {
    pub ram: Vec<u8>,
    pub clint: Clint<T>,
    // ...
}

impl BusReader for Bus {
    fn read32(&self, addr: u32) -> Result<u32, BusException> {
        match addr {
            0x1100bffc => Ok(self.clint.read(addr & 0xffff)),
            0x1100bff8 => Ok(self.clint.read(addr & 0xffff)),
            _ => { ... }
        }
    }
}

let mut f = File::open(dtb)?;
let len = f.metadata()?.len();
let ptr = ram_size as u64 - len;
// dtbをRAMの最後尾にlaodする
f.read_exact(&mut ram[(ptr as usize)..(ptr + len) as usize])?;

core.a0(0x00) // hart id
    .a1(ptr) // ref to dtb
    .pc(pc);

let mut ram = vec![0u8; ram_size];
let mut f = File::open(args.image_file_path)?;
let len = f.metadata()?.len();
// RAMの先頭にimageをloadする
f.read_exact(&mut ram[..len as usize])?;

    fn write32(&mut self, addr: u32, v: u32) -> Result<(), BusException> {
        match addr {
            // ...
            0x10000000..=0x100000ff => {
                let addr = addr & 0xffff;
                self.serial.write(addr, v);
            }
            // ...
        };
        Ok(())
    }

impl device_interfaces::SerialInterface for Uart {
    fn write(&self, addr: u32, v: u32) {
        if addr == 0x000 {
            let c = char::from_u32(v).expect("...");
            print!("{}", c);
            std::io::stdout().flush().expect("...");
        }
    }
}

impl device_interfaces::SerialInterface for Uart {
    fn read(&self, addr: u32) -> u8 {
        match addr {
            // データがあれば最下位bitを1とする
            0x0005 => 0x60 | if is_keydown() { 1 } else { 0 },
            0x0000 if is_keydown() => read_key() as u8,
            _ => 0,
        }
    }
}

extern "C" {
    fn elapsed_us() -> usize;
    fn tx(s: u32);
    fn rx() -> u32;
    fn keydown() -> bool;
}

struct Elapsed;

impl device_interfaces::TimerDriver for Elapsed {
    fn as_micros(&self) -> u64 {
        unsafe { elapsed_us() as u64 }
    }
}

struct Term;

impl device_interfaces::SerialInterface for Term {
    fn read(&self, addr: u32) -> u8 {
        match addr {
            0x0000 if unsafe { keydown() } => unsafe { rx() as u8 },
            0x0005 => 0x60 | if unsafe { keydown() } { 1 } else { 0 },
            _ => 0,
        }
    }

    fn write(&self, addr: u32, v: u32) {
        if addr == 0x000 {
            // txを介してmain threadにmessageを投げる
            unsafe {
                tx(v);
            }
        }
    }
}

#[no_mangle]
pub extern "C" fn start() {
    let ram_size = 640 * 1024 * 1024;
    let mut ram = vec![0u8; ram_size];

    // 今回はWasmに埋めてしまう
    let bin = include_bytes!("../../fixtures/linux.bin");
    let dtb = include_bytes!("../../fixtures/default.dtb");

    ram[0..bin.len()].copy_from_slice(bin);
    let dtb_ref = ram_size - dtb.len();
    ram[dtb_ref..dtb_ref + dtb.len()].copy_from_slice(dtb);

    let clint = core::clint::Clint::new(Elapsed);
    let term = Term;
    let bus = core::bus::Bus::new(ram, clint, term);
    let sleep = |_u: std::time::Duration| {};
    core::start(bus, RAM_START, dtb_ref as u32 + RAM_START, &sleep);
}